1. Field of the Invention
The present invention relates to a power conversion system including a plurality of conversion units having substantially the same structure and operating in parallel to supply a.c. power to a common load.
2. Description of the Prior Art
FIG. 4 shows a conventional inverter system of the prior art disclosed in Japanese Published Patent Applications Nos. 53-36137 and 56-13101. In the figure, #1 and #2 inverter units 1 and 2 having the same construction are operated in parallel to supply power through an output bus 3 to a load 4.
The inverter unit 1 comprises an inverter circuit 100, an output transformer 101, and a reactor 102 and a capacitor 103 constituting a filter. The inverter unit 1 converts power supplied from a d.c. power source 5 into a.c. power, which is conducted through an output switch 104 to the output bus 3.
Next, the operation of the above inverter system will be described. When the parallel operation of the two inverter units 1 and 2 is necessary, the output current I.sub.1 of the #1 inverter unit 1 is detected as a signal I.sub.1a by a current transformer (CT) 106, and in the same way the output current of the #2 inverter unit 2 is detected as a signal I.sub.2a. A lateral current detector 107 provided in the inverter unit 1 evaluates the difference between I.sub.1a and I.sub.2a to produce a signal .DELTA.I representing a lateral current flowing between the units. A phase shifter 108 produces two perpendicularly-intersecting voltage vectors E.sub.A and E.sub.B, and arithmetic circuits 109 and 110 evaluate the reactive power component .DELTA.Q and effective power component .DELTA.P based on the detected signal .DELTA.I and the respective voltage vectors E.sub.A and E.sub.B. Based on the signals provided by a voltage setting circuit 111 and voltage feedback circuit 112, a voltage control circuit 113 operates on a pulse width modulation (PWM) circuit 114 to implement pulse width modulation for the inverter circuit 100, thereby controlling the output voltage.
The above-mentioned reactive power component .DELTA.Q is given to the voltage control circuit 113 as a supplementary signal, so that the reactive power component .DELTA.Q is nullified by regulating the inverter output voltage within a few percent range. The effective power component value .DELTA.P is fed through an amplifier 115 constituting a PLL circuit to a reference oscillator 105 so that its output frequency is adjusted finely, thereby controling the phase of inverter output voltage to nullify the effective power component .DELTA.P.
By controlling the inverter output voltage and phase so as to nullify both of the reactive and effective power components .DELTA.Q and .DELTA.P, no lateral current flows between the two inverter units and the load is shared stably by the units.
The conventional inverter system employing the parallel operation system as described above, needs a test as to whether it operates normally as expected, and the only test method is to operate the system by connecting the first and second inverter units 1 and 2 to the output bus 3 in FIG. 4. However, as is known in the art, the usual inverter has an overcurrent withstanding capability of only 150% of the rated current in general, and therefore it is extremely difficult to test the control circuit and adjust the response of control while actually operating the system of FIG. 4.
In practice, individual components of the control circuit shown in FIG. 4 are tested and adjusted completely and wiring between the components is checked before conducting the running test for the overall system shown in FIG. 4. Even with such a prudent procedure for the parallel operation, it frequently occurs that an unexpected fault causes an excessive lateral current and the inverter fails to commutate, resulting in a damage to the system. This implies difficulties in investigating a fault (particularly an intermittent fault such as that caused by a faulty electric contact) and also in conducting a periodical maintenance service.
In such a control instability is caused by an unexpected harmonic lateral current included in the output current I.sub.1 of each inverter unit; harmonic current in large proportions including in the detected lateral current signal .DELTA.I disturbs the detection of the intersecting current components, causing the instability. In this case, the output filter capacitor 103 provided for each inverter unit forms a resonance circuit in conjunction with other capacitors of other inverter units through the inductance of output bus 3. The resonance frequencies, which depend on the length of wiring, are in many cases relatively high above the seventh harmonic. Harmonics created by any of the parallel-connected inverter units resonate in this resonance circuit, yielding a very large harmonic lateral current. In the case of synchronized rectifying circuits used as the arithmetic circuits 109 and 110, the harmonic lateral current produces the following signals. FIG. 5(b) and (c) shows the signals .DELTA.P and .DELTA.Q derived from a fundamental lateral current signal .DELTA.I shown in FIG. 5(a) through the synchronized rectification. Assuming a case that the signal .DELTA.I is not of the fundamental component, but a .DELTA.I of the fifth harmonic component exists as a harmonic lateral current as shown by (d) in FIG. 5. Synchronized rectification for this signal yields a .DELTA.P component signal shown by (e) and a .DELTA.Q component signal shown by (f) in FIG. 5. The .DELTA.Q signal averages out to zero, while the .DELTA.P signal remains in its positive parts as shown by hatching. A positive .DELTA.P signal indicates an excessive share of effective power by the associated inverter unit, causing the PLL amplifier 115 to lower temporarily the oscillation frequency so as to produce a lag phase of the inverter unit 1. The harmonic lateral current shown at (d) in FIG. 5 has an opposite phase for the inverter unit 2, causing its .DELTA.P signal to be negative, and the amplifier 115 in the inverter unit 2 operates to lead the phase of the inverter unit 2. In actual operation, however, there is no lateral current of the fundamental component between the inverter units 1 and 2, requiring no adjustment for the phase difference, and the above-mentioned PLL circuit operation in response to the .DELTA.P signal is erroneous, resulting in an increased lateral current of the fundamental component and eventually in the instability of parallel operation. Although in the exemplary case shown by (d), (e) and (f) in FIG. 5 the fifth harmonic wave has a phase relationship with the fundamental wave as shown, in actual operation various phase relationships occur, so both the .DELTA.P and .DELTA.Q signals will have various values in even positive and negative. Therefore, instability arises not only in the phase control, but also in the voltage control due to an erroneous .DELTA.Q signal. Although the example of FIG. 5 deals with the fifth harmonic wave for the sake of simplicity, it will be apparent that abnormal .DELTA.P and .DELTA.Q signals can equally result generally for the nth harmonic wave. In general, the nth harmonic wave exerts an influence of 1/n gain on the system as a result of synchronized rectification, disturbing the control system of a parallel operating inverter system as shown in FIG. 4.
In order to overcome the foregoing problems, there is known a method of multiplicatiion between the signal .DELTA.I and sinusoidal E.sub.A and E.sub.B signals using multipliers as arithmetic circuits 109 and 110. However, multipliers are generally complex in construction, and therefore relatively susceptible to failure, and expensive. On this account, it is very desirable for the system as shown in FIG. 4 to employ simpler and more reliable synchronized rectification circuits.